later annotation · v1.4Δτ, the exponent contrast quoted on this page, is invariant to affine rescalings of the error but not to monotone non-affine ones — under log(1+err) and √err its sign reverses. It is retained here as the pre-registered test it was, and the paper now leads with a model-free floor-referenced contrast instead. See coordinate-audit.html.

Project ASPECT-D · Results · outcome class S1 · generated 2026-08-06 14:24 UTC

Refinement steps buy intelligibility, not identity — measured

Per-metric (width, depth, steps) scaling for masked-diffusion TTS. Every number on this page comes from results/artifacts/runs.csv, results/artifacts/fits.json or results/artifacts/c_layer.json. Declared outcome class: S1 — test-time scaling is metric-selective — refinement steps buy intelligibility far faster than speaker identity.

Headline Δτ = τ_WER − τ_SIM = 0.110, 95% run-level bootstrap CI [0.092, 0.131] → H-D2 supported. κ_WER = 3.000, CI [3.000, 3.000] → H-D3 not supported. Δρ = ρ_SIM − ρ_WER = 0.174, CI [-0.711, 0.388] → H-D1 not supported. Power gate G4: passed. Surface: 225 rows = 15 configs × 3 seeds × 5 T values, 400 eval items each.

§1What was run

Item	Value
Training data	2000 h Emilia-EN, 792,064 clips, 64,680 speakers (≥4,000 required), 200 held-out speakers
sec_per_char (Phase 0, median over 10,000 clips)	0.06020
Recipe	coarse-to-fine (grid.json backbone.training_objective)
T semantics	steps per level, NFE = 8T (grid.json sampler_frozen.T_definition)
μP base LR (chosen at G1)	0.004
Completed runs	45
Compute used	142.9 / 500 B200-h
SIM-o model	wavlm_large_sv_unispeech(seed-tts-eval)
Eval-harness sanity (G0c, ground-truth audio)	WER 3.4% · same-speaker SIM 0.701 · cross-speaker SIM 0.034

§2The step axis (Part B — primary)

M_sep: err_m(w,d,T) = E + A·w^−α + B·d^−β + C·T^−τ · M_sub: err_m = E + A·w^−α + B·(d·T^κ)^−β

Metric	α (width)	β (depth)	τ (steps)	τ 95% CI	κ	κ 95% CI	ΔAICc(sub−sep)	ΔAICc(full−N)
WER	1.574	2.040	0.836	[0.825, 0.851]	3.000	[3.000, 3.000]	69.3	-15.5
SIM-o	0.919	0.553	0.726	[0.709, 0.744]	3.000	[3.000, 3.000]	71.3	-5.5

Δτ = 0.110, 95% CI [0.092, 0.131] — excludes 0. Bootstrap: run-level, 2000/2000 replicates converged, RNG 7331. Saturation steps, normalised to each metric's own total T-gain (affine-invariant): T* = 16 for both WER and SIM-o. The raw-scale variant of this statistic (WER 16, SIM-o 8) is withdrawn — the 5% band is 0.67% of WER's range but 11.96% of SIM's, a 17.9× difference in strictness, so the apparent gap was an artifact of scale and not of the models' behaviour.

step_curves.svg — Error vs T per metric, every config, normalised to its T=1 value; thick lines are grid means. The per-metric dotted T* markers still drawn in this SVG are computed on each metric's own raw scale and are not comparable across metrics; the figure is being regenerated without them. On the affine-invariant statistic T* = 16 for both metrics.

substitution_plane.svg — Iso-WER contours in (log T, log d) from M_sub with the fitted slope −κ, and the iso-latency line 8·T·d = const from the measured c_layer.

aniso_contours_T16.svg — Fitted anisotropy surface at T=16 with the measured config means overlaid; ρ = α/β per metric.

extrapolation.svg — H-D4: the two smaller budgets predict the largest budget under M_full and under the N-only model.

§3Anisotropy at T=16 (Part A — secondary)

Metric	α	β	ρ=α/β	E	ΔAICc(full−N)	shape matters (ΔAICc ≤ −4)
WER	1.338	1.935	0.692	0.109	-15.5	yes
SIM-o	0.893	1.031	0.866	0.565	-5.5	yes

Δρ = ρ_SIM − ρ_WER = 0.174, CI [-0.711, 0.388]. H-D4 (extrapolation to the largest budget): WER MAPE 20.2% under M_full vs 20.4% under the N-only model; SIM-o 2.4% vs 2.2%.

§4Budget-constrained minima on the measured T ≤ 16 grid

Serial latency per utterance = 8·T·d·c_layer(w) (grid.json latency_model) with c_layer measured on NVIDIA B200 at batch 1: w=256: 0.497 ms, w=320: 0.510 ms, w=384: 0.514 ms, w=448: 0.500 ms, w=512: 0.493 ms, w=640: 0.506 ms, w=768: 0.498 ms, w=832: 0.499 ms, w=960: 0.493 ms, w=1152: 0.502 ms. For each budget the table gives the (w, d, T) point of the measured grid that minimises the fitted M_sep prediction subject to the budget. Caveat: T is censored at the grid maximum of 16, and every optimum at ≥ 1000 ms sits exactly on that boundary, so this table supports no depth-versus-steps ordering — on the extended T ≤ 64 grid the ordering reverses. No allocation rule is claimed here.

Metric	Budget (ms)	Best config	w	d	T	latency (ms)	predicted err
WER	200	B1	832	6	8	192	0.3169
WER	500	C2	960	12	8	379	0.2267
WER	1000	C2	960	12	16	757	0.1398
WER	2000	B5	384	30	16	1974	0.1159
WER	4000	C5	512	36	16	2272	0.1142
SIM	200	B1	832	6	8	192	0.6518
SIM	500	C2	960	12	8	379	0.6299
SIM	1000	C2	960	12	16	757	0.6133
SIM	2000	C4	640	26	16	1684	0.6071
SIM	4000	C4	640	26	16	1684	0.6071

§5Measured surface

config	w	d	N	T	WER	SIM-o	DegenRate	UTMOS	val loss	latency (ms)
A1	640	4	19.7M	1	112.8%	0.198	39.3%	1.52	4.6377	16
A1	640	4	19.7M	2	102.0%	0.249	15.5%	1.86	4.6377	32
A1	640	4	19.7M	4	77.6%	0.289	3.8%	2.32	4.6377	65
A1	640	4	19.7M	8	61.3%	0.315	1.6%	2.64	4.6377	130
A1	640	4	19.7M	16	53.9%	0.327	0.7%	2.84	4.6377	259
A2	448	8	19.3M	1	117.2%	0.202	41.8%	1.52	4.5818	32
A2	448	8	19.3M	2	86.5%	0.267	11.0%	1.90	4.5818	64
A2	448	8	19.3M	4	50.8%	0.311	1.2%	2.40	4.5818	128
A2	448	8	19.3M	8	34.7%	0.338	0.3%	2.72	4.5818	256
A2	448	8	19.3M	16	28.4%	0.348	0.1%	2.91	4.5818	512
A3	384	12	21.2M	1	113.9%	0.202	40.8%	1.52	4.5661	49
A3	384	12	21.2M	2	83.2%	0.265	9.8%	1.91	4.5661	99
A3	384	12	21.2M	4	34.6%	0.319	1.1%	2.45	4.5661	197
A3	384	12	21.2M	8	19.7%	0.346	0.0%	2.77	4.5661	395
A3	384	12	21.2M	16	15.9%	0.360	0.2%	2.96	4.5661	789
A4	320	18	22.1M	1	115.4%	0.203	39.9%	1.52	4.5740	74
A4	320	18	22.1M	2	77.1%	0.266	7.8%	1.93	4.5740	147
A4	320	18	22.1M	4	30.5%	0.320	0.4%	2.48	4.5740	294
A4	320	18	22.1M	8	17.8%	0.347	0.0%	2.79	4.5740	588
A4	320	18	22.1M	16	13.6%	0.359	0.0%	2.94	4.5740	1176
A5	256	24	18.9M	1	115.8%	0.194	38.2%	1.52	4.6112	95
A5	256	24	18.9M	2	76.2%	0.260	9.5%	1.91	4.6112	191
A5	256	24	18.9M	4	34.2%	0.313	0.8%	2.43	4.6112	382
A5	256	24	18.9M	8	20.8%	0.339	0.2%	2.76	4.6112	763
A5	256	24	18.9M	16	15.3%	0.351	0.2%	2.92	4.6112	1527
B1	832	6	49.9M	1	112.1%	0.212	39.4%	1.54	4.5506	24
B1	832	6	49.9M	2	85.1%	0.269	9.4%	1.93	4.5506	48
B1	832	6	49.9M	4	49.8%	0.320	1.7%	2.43	4.5506	96
B1	832	6	49.9M	8	33.7%	0.345	0.4%	2.75	4.5506	192
B1	832	6	49.9M	16	27.8%	0.361	0.1%	2.93	4.5506	383
B2	640	10	49.2M	1	113.9%	0.208	43.2%	1.51	4.5049	40
B2	640	10	49.2M	2	76.6%	0.282	9.0%	1.94	4.5049	81
B2	640	10	49.2M	4	33.6%	0.341	0.2%	2.48	4.5049	162
B2	640	10	49.2M	8	20.9%	0.371	0.2%	2.81	4.5049	324
B2	640	10	49.2M	16	16.0%	0.381	0.0%	2.98	4.5049	648
B3	512	16	50.3M	1	114.9%	0.212	40.3%	1.52	4.4971	63
B3	512	16	50.3M	2	72.9%	0.293	7.5%	1.96	4.4971	126
B3	512	16	50.3M	4	26.8%	0.347	0.3%	2.53	4.4971	252
B3	512	16	50.3M	8	16.6%	0.376	0.0%	2.83	4.4971	505
B3	512	16	50.3M	16	11.9%	0.388	0.1%	3.00	4.4971	1010
B4	448	22	53.0M	1	108.5%	0.212	42.4%	1.53	4.5105	88
B4	448	22	53.0M	2	71.6%	0.287	7.3%	1.97	4.5105	176
B4	448	22	53.0M	4	28.6%	0.347	0.2%	2.53	4.5105	352
B4	448	22	53.0M	8	16.1%	0.375	0.1%	2.84	4.5105	704
B4	448	22	53.0M	16	12.0%	0.382	0.1%	2.99	4.5105	1408
B5	384	30	53.1M	1	112.8%	0.209	40.9%	1.52	4.5198	123
B5	384	30	53.1M	2	69.1%	0.285	7.2%	1.96	4.5198	247
B5	384	30	53.1M	4	27.4%	0.345	0.1%	2.52	4.5198	493
B5	384	30	53.1M	8	16.0%	0.372	0.2%	2.82	4.5198	987
B5	384	30	53.1M	16	11.5%	0.375	0.1%	2.98	4.5198	1974
C1	1152	8	127.4M	1	112.8%	0.216	38.9%	1.54	4.5039	32
C1	1152	8	127.4M	2	79.1%	0.289	8.8%	1.97	4.5039	64
C1	1152	8	127.4M	4	35.1%	0.338	0.4%	2.50	4.5039	128
C1	1152	8	127.4M	8	22.5%	0.367	0.1%	2.81	4.5039	257
C1	1152	8	127.4M	16	17.1%	0.373	0.2%	2.98	4.5039	514
C2	960	12	132.7M	1	115.4%	0.216	38.5%	1.53	4.5035	47
C2	960	12	132.7M	2	77.9%	0.286	6.3%	1.96	4.5035	95
C2	960	12	132.7M	4	36.7%	0.341	0.7%	2.49	4.5035	189
C2	960	12	132.7M	8	23.2%	0.366	0.2%	2.81	4.5035	379
C2	960	12	132.7M	16	18.9%	0.373	0.2%	2.97	4.5035	757
C3	768	18	127.4M	1	114.3%	0.221	39.5%	1.53	4.4879	72
C3	768	18	127.4M	2	76.3%	0.296	8.3%	1.96	4.4879	143
C3	768	18	127.4M	4	31.6%	0.353	0.7%	2.51	4.4879	287
C3	768	18	127.4M	8	18.4%	0.381	0.1%	2.83	4.4879	573
C3	768	18	127.4M	16	14.3%	0.392	0.0%	2.98	4.4879	1147
C4	640	26	127.8M	1	115.3%	0.215	41.7%	1.52	4.4889	105
C4	640	26	127.8M	2	73.1%	0.290	7.2%	1.97	4.4889	211
C4	640	26	127.8M	4	28.8%	0.352	0.2%	2.52	4.4889	421
C4	640	26	127.8M	8	17.4%	0.381	0.0%	2.84	4.4889	842
C4	640	26	127.8M	16	13.4%	0.390	0.1%	3.01	4.4889	1684
C5	512	36	113.3M	1	112.1%	0.219	40.8%	1.52	4.4867	142
C5	512	36	113.3M	2	67.6%	0.293	6.5%	1.97	4.4867	284
C5	512	36	113.3M	4	25.0%	0.354	0.3%	2.54	4.4867	568
C5	512	36	113.3M	8	13.9%	0.379	0.1%	2.86	4.4867	1136
C5	512	36	113.3M	16	9.9%	0.388	0.0%	3.02	4.4867	2272

§6Gate, cut and calendar history

Gate G6 — pass

{"passes": true, "today": "2026-08-06", "next_milestone": "M1_env_mup_done", "due": "2026-08-12", "hard_wall": "2026-08-29", "days_to_wall": 23}

Gate G5 — pass

{"passes": true, "used_gpu_hours": 171.8436410319141, "occupancy_gpu_hours": 64.9795189098517, "mean_hours_per_run": 3.6117848808117854, "runs_remaining": -15, "projected_total": 194.3436410319141}

Gate G1 — pass {"argmin_w256": 0.004, "argmin_w640": 0.002, "passes": true, "when": "2026-08-05 23:47 UTC"}

Gate G1b — pass {"argmin_d4": 0.002, "argmin_d24": 0.002, "passes": true, "when": "2026-08-05 23:47 UTC"}

Gate G2 — pass

{"passes": true, "checks": {"WER(C3,T=16) <= 0.30": {"pass": true, "value": 0.11250733636706733}, "WER(A3,T=16) <= 0.65": {"pass": true, "value": 0.1612674587067795}, "SIM-o(C3,T=16) >= 0.30": {"pass": true, "value": 0.4081370605202392}, "SIM-o(C3,T=16) >= cross baseline + 0.15": {"pass": true, "value": 0.4081370605202392}, "DegenRate(C3,T=16) <= 0.40": {"pass": true, "value": 0.0}}, "cross_speaker_baseline": 0.03381083719432354, "T_FLAT": false, "wer_C3_T1": 1.1411705989383842, "wer_C3_T16": 0.11250733636706733}

Gate G3 — pass

{"passes": true, "configs_with_all_seeds": 15, "threshold": 12, "per_config_seeds": {"A1": [0, 1], "A2": [0, 1], "A3": [0, 1], "A4": [0, 1], "A5": [0, 1], "B1": [0, 1], "B2": [0, 1], "B3": [0, 1], "B4": [0, 1], "B5": [0, 1], "C1": [0, 1], "C2": [0, 1], "C3": [0, 1], "C4": [0, 1], "C5": [0, 1]}, "restarts": {}, "when": "2026-08-06 09:53 UTC"}

Gate G_sampler_integrity — pass

{"passes": true, "n_runs": 45, "n_failing": 0, "differing_cell_fraction_range": [0.9819560669456067, 0.9888859832635983], "when": "2026-08-06 14:18 UTC"}

Gate G4 — pass {"passes": true, "n_budgets_passing": {"wer": 3, "sim": 3}, "when": "2026-08-06 14:21 UTC"}

Cuts applied: none — no compute or calendar cut was triggered. Flags: none.

Protocol: protocol.html · theory: motivation.html · implementation: implementation.html · decision: DECISION.md · trail: LOG.md.